The 68HC12 ( or HC12 for short) is a microcontroller family from Freescale Semiconductor. Originally introduced in the mids, the architecture is an. Has several new addressing modes added. • Accesses additional memories externally. Here is an overview of the HCS12 CPU architecture. The HCS12 CPU is. COM/SEMICONDUCTORS. HCS Microcontrollers. S12CPUV2/D. Rev. 0 In the M68HC12 and HCS12 architecture, all memory and input/output. (I/O) are.

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The following are all equivalent: Introduction to Assembly Language.

Control Unit Basic Architecture. These operands are the data usually numbers to be operated on. All instructions must have an op code.

EET Unit 2 HCS12 Architecture – ppt video online download

The pound sign indicates immediate addressing. Write an instruction sequence to create a delay of 10 sec. The instruction summary tells you the possible addressing modes for any instruction. Data Sheets show more. B6 30 00 Ramadan Al-Azhar University Lecture 3.

Condition Codes These columns show how each instruction affects the bits in the Condition Code Register. Examples, using 8 bits: Trace Recording for Embedded Systems: Students not only develop a strong foundation of Assembly language programming, they develop a comprehensive understanding of HCS12 interfacing.

Therefore, within the range of possible addresses, only some can be used by your programs. This book can also be used by practicing technicians, hardware engineers, computer scientists, and hobbyists. To use this website, you must agree to our Privacy Policyincluding cookie policy. The other registers X, Y, and SP sometimes serve as general-purpose registers and sometimes perform specific functions. In doing so, they develop the knowledge background they need to understand the design and interfacing of microcontroller-based embedded systems.


Some abbreviations used in this column: ABA This table uses many abbreviations and special symbols. Each instruction performs a simple operation and executes quickly.

Extended — bit absolute address in the instruction.

System block diagram A8 version. Calculating Branch Destinations – Valid range: To make this website work, we log user data and share it with processors. For example, instead of specifying architecfure number to be loaded right in the instruction itself, maybe we want to load the number from a particular memory location into ACCA.

Review questions are provided at the end of each section to reinforce the main points of the section. The ABA instruction always uses the inherent addressing mode. In this notation, the leftmost bit is the sign bit.

Share buttons are a little bit lower. Operation This column explains the operation that the instruction performs. PC and CCR are special-purpose registers that always perform specific functions: Some instructions operate on Accumulator A or Accumulator B. Also called PC-Relative addressing. Assembly language contains many mnemonics, which are abbreviations for actions that we want to perform.


HCS12 Microcontrollers and Embedded Systems

A memory location cannot be the destination of an ADD instruction. A memory map shows which memory addresses architectuure reserved, and which are available for your use. Home Contact Us Help Free delivery worldwide. Check out the top books of the year on our page Best Books of But there are other ways to specify the operand. Feedback Privacy Policy Feedback. Microprocessor and Microcontroller Based Systems Instructor: By using our website you agree to our use of cookies.

These two can also be regarded as forming a single bit accumulator named D. We think you have liked this presentation.

HCS12 ARCHITECTURE Razvan Bogdan Embedded Systems.

But only some instructions affect these flag bits: To use this website, you must agree to our Privacy Policyincluding cookie policy. Access Detail This column shows how many cycles each instruction takes to execute, and what happens during each of those cycles.

This happens when either: Arrchitecture presentations Profile Feedback Log out. To make this website work, we log user data and share it with processors.

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